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RM0008
13.4.20
Advanced-control timers (TIM1&TIM8)
Bits 4:0 DBA[4:0] : DMA base address
This 5-bits vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
TIM1&TIM8 DMA address for full transfer (TIMx_DMAR)
Address offset: 0x4C
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMAB[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 DMAB[15:0] : DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address
configured in TIMx_DCR register, DMA index is the offset automatically controlled by the
DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.
13.4.21
Table 74.
TIM1&TIM8 register map
TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table
below:
TIM1&TIM8 register map and reset values
Offset
Register
0x00
TIMx_CR1
Reserved
CKD
[1:0]
CMS
[1:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0x04
TIMx_CR2
Reserved
MMS[2:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x08
TIMx_SMCR
Reserved
ETPS
[1:0]
ETF[3:0]
TS[2:0]
SMS[2:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0C
TIMx_DIER
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x10
TIMx_SR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0x14
TIMx_EGR
Reserved
Reset value
0
0
0
0
0
0
0
0
Doc ID 13902 Rev 9
317/995
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